Future electronic systems will continue to require both ever increasing speed and decreasing power consumption. To attain higher speeds and maintain low power consumption, integrated circuit (IC) chips, as one of the principle components of electronic systems, will need to operate at ever higher frequencies while consuming as little power as possible. As device sizes decrease to increase speed and reduce chip size, increased static power consumption will become a major hurdle to attaining low power consumption goals, especially for IC chips manufactured using CMOS technology. Static power consumption is the power consumed by circuits, and more particularly, individual devices that are not actively changing states, i.e., the transistors are in a steady off state. Up until now, static power consumption in CMOS technology has been negligible. But the continued shrinking of device sizes will change this.
Continuing process advancements have allowed for reductions in critical dimensions in CMOS manufacturing. IC device dimensions have now or are about to reach a critical point where static power consumption will become a major concern unless new techniques are implemented to avoid unacceptable static power consumption levels. As device sizes have shrunk there has been a reduction in power supply voltage (Vdd). While lower Vdd corresponds to lower dynamic power consumption, it also reduces the speed of the device. To maintain or increase device speed, efforts have been pursued to reduce the threshold voltage (Vth) of transistors within a given process. However, the subthreshold voltage current, or leakage current, of a transistor exponentially increases with any Vth decrease. At prior larger device dimensions, this exponential leakage current increase was still negligible. But, at current and future device dimension sizes, this exponential increase in leakage current will result in a rapid and noticeable increase in static power consumption. Thus, without employing a new approach, the designer may be required to make unacceptable trade off decisions between speed and power consumption.
To counteract this increasing power consumption problem, it would be possible to increase the voltage threshold level of the transistors; however, this would have negative impacts on the transistor speed or frequency that the device could be used. Furthermore, increasing Vth can introduce other problems because of noise margins that must be maintained within the device. It has been found that increasing Vth to more than Vdd/3 will negatively impact the functionality of the device.
As device sizes continue to shrink, this static power consumption issue will become important for the entire semiconductor industry. It is particularly important now for makers of devices such as programmable logic devices (PLDs) that contain large numbers of transistors on a single die that, after programming, may remain in a static off state.
A PLD is an integrated circuit comprised of an array of configurable logic elements (CLEs) surrounded by a general routing matrix (GRM) with multiple input/output ports. In general, PLDs include programming elements such as static random access memory cells (SRAMs), antifuses, EPROMs, Flash cells, or EEPROMS. These memory elements are used to control the functions performed by the CLEs, the routing of signals in the GRM between CLEs and their input/output ports, and also control the functionality of the input/output ports. Recently, PLD makers have trended toward providing a large number of tri-state drivers to support high fan out signals to be routed in the GRM. A PLD is designed to perform any logic function required by a user.
In practice, once a PLD user designs the function to be implemented by the PLD, and the PLD is programmed to perform the function, a large number of the resources available on the PLD are unused. Thus, the PLD may have a large percentage of transistors that are not being used at any given time. XILINX™, a leading manufacturer of PLDs, makes a variety of PLD known as a field programmable gate array (FPGA). Analysis of typical designs used by users of XILINX™ FPGAs shows that anywhere from 60 to 90 percent of the FPGA resources are typically unused. These unused resources are in a static mode and thus as static power consumption increases for a given process the FPGA and PLD in general is likely to see large increases in overall power consumption.
It is desirable then to implement new circuit techniques that will operate at increased speeds and reduce leakage current in static CMOS devices and thereby reduce IC chip power consumption.